1. Field of the Invention
The present invention relates to a sustain signal driver circuit for a capacitive display panel and, more particularly, to a sustain signal driver circuit for minimizing power loss when driving a capacitive load.
2. Description of the Prior Art
Plasma display panels (PDPs) are well known in the art and include a front plate with horizontal electrode pairs having a capacitance there between. The electrode pairs are covered by a glass dielectric layer and a magnesium oxide (MgO) layer. A back plate supports vertical barrier ribs and plural vertical column electrodes. The individual column electrodes are covered with red, green, or blue phosphors, as the case may be, to provide for a full color display. The front and rear plates are sealed together and the space there between is filled with an electrically dischargeable gas.
A pixel is defined by an intersection of an electrode pair on the front plate and three column electrodes for red, green, and blue, respectively, on the back plate. The electrode pair on the front panel has a region of overlap therebetween. The width of the electrode pair and the thickness of the dielectric glass over the electrode pair determine the pixel's discharge capacitance, which in turn influences the discharge power and therefore the brightness of the pixel. A number of discharges are controlled to provide a desired brightness for the panel.
Detailed descriptions of the structure and operation of gas discharge panels are set forth in U.S. Pat. No. 3,559,190 to Bitzer, et al. and in U.S. Pat. No. 4,772,884 to Weber et al.
The typical operation of an AC plasma display involves applying alternating sustain pulses to the front panel electrode pair. Each sustain pulse consists of a positive going resonant transition, activation of a pull up driver to source a gas discharge current, a negative going resonant transition, and activation of a pull down driver. The sustain pulse is applied to a first one of the electrodes in the pair, and then, the same sequence is applied to the second electrode in the pair. The gas discharge occurs at the completion of the rising transition.
Display devices such as plasma displays require high speed charging and discharging of the capacitive loads of the pixels with relatively high voltages, e.g., 50 to 200 volts, over a broad range of frequencies, e.g., 10 KHz to 500 KHz. Energy recovery sustainers have been developed for plasma displays to enable recovery of energy used to charge and discharge a panel's capacitance. As AC plasma displays have grown in size and as operating voltages have increased, the needs of increased switching efficiency and precise control of the turn-on of output drivers has become critical.
U.S. Pat. No. 5,081,400 to Weber et al. (hereinafter “the Weber et al. '400 patent”) discloses an energy recovery circuit. U.S. Pat. No. 5,642,018 to Marcotte (hereinafter “the Marcotte '018patent”) discloses using a signal derived from an energy recovery inductor to precisely control the turn-on of the output drivers for an energy recovery circuit.
U.S. Pat. No. 5,828,353 to Kishi et al. discloses a circuit for producing a pulse having asymmetrical rising and falling transistions. The circuit includes an application inductor in parallel with a recovery inductor. The application inductor influences only the rising transition, and the recovery inductor influences only the falling transition.
With regard to a switch or transistor as described herein, the terms “closed” and “on” correspond to a state where current can be conducted through the switch or transistor, and the terms “open” and “off” correspond to a state where current cannot be conducted through the switch or transistor.
FIG. 1 shows an idealized schematic of a circuit that includes a prior art sustain driver 100. Sustain driver 100 includes four switches, S1, S2, S3 and S4, which are controlled so that sustain driver 100 progresses through four successive switching states, i.e., State 1, State 2, State 3 and State 4. Sustain driver 100 outputs a sustain pulse, which is represented as a panel voltage Vp.
A control signal is provided from a source as in input to sustain driver 100 to control the progression of States 1-4. The control signal is a logic level signal, e.g., 0-5 volts, having a leading rising edge and a lagging falling edge. Each idealized circuit described herein, e.g., sustain driver 100 in FIG. 1, is driven by such a control signal, but the source is shown only in the detailed circuit views, e.g., source 12 in FIG. 3.
FIG. 2 shows, for the circuit of FIG. 1, a waveform of voltage Vp and a waveform of a current IL through an inductor L. The waveforms of FIG. 2 are those expected as switches S1-S4 are opened and closed through the progression of States 1-4.
Sustain driver 100 operates with a power supply voltage Vcc. Assume that prior to State 1 a recovery voltage Vss is at Vcc/2, Vp is at zero, S1 and S3 are open, and S2 and S4 are closed. A capacitance Cp is the panel capacitance as seen by sustain driver 100. A recovery capacitance Css must be much greater than Cp to minimize a variation of Vss during States 1 and 3. The reason that Vss is at Vcc/2 will be explained, below, after the switching operation is explained.
State 1. S1 is closed, S2 is opened, S3 remains open, as it was prior to State 1, and S4 is opened. With S1 closed, a diode D1 is forward biased. Inductor L and Cp form a series resonant circuit, and a “forcing” voltage of Vss=Vcc/2 is applied across L and Cp. During State 1, current IL charges Cp so that Vp rises to Vcc as energy is transferred from Css to Cp. By the end of State 1, IL falls to zero, and diode D1 becomes reverse biased. In State 1, sustain driver 100 provides a leading rising edge of the sustain pulse.
State 2. S3 is closed. Through S3, Vp is clamped at Vcc and a current path is provided from Vcc for any “ON” pixels in the panel. When a pixel is in the ON state, its periodic discharges provide a substantial short circuit across an ionized gas. The current required to maintain the discharge is supplied from Vcc. The discharge/conduction state of a pixel is represented by icon 10.
State 3. S1 is opened, S2 is closed, and S3 is opened. With S2 closed, D2 is forward biased and inductor L and capacitance Cp again form a series resonant circuit, with the voltage across inductor L equal to Vss=Vcc/2. However the polarity of the voltage across L is reverse as compared to that of State 1, causing a negative flow of current IL. During State 3 Vp then falls to ground as energy previously stored in inductor L is returned to Css. By the end of State 3, IL reaches zero, and D2 becomes reverse biased. In State 3, sustain driver 100 provides a falling, lagging edge of the sustain pulse.
State 4. S4 is closed. Through S4, Vp is clamped to ground. On the opposite side of the plasma panel, another sustain driver 105, which is identical to sustain driver 100, drives the opposite side of the panel to Vcc. If any pixels are “ON”, then a discharge current flows through S4.
It was assumed above that Vss remains stable at Vcc/2 during charging and discharging of Cp. The reasons for this are as follows. If Vss were less than Vcc/2, then on the rise of Vp, when S1 is closed, the forcing voltage would be less than Vcc/2. Subsequently, on the fall of Vp, when S2 is closed, the forcing voltage would be greater than Vcc/2. Therefore, on average, current would flow into Css. Conversely, if Vss were greater than Vcc/2, then on average, current would flow out of Css. Thus, the stable voltage at which the net current into Css is zero, is Vcc/2. In fact, on power up, as Vcc rises, if sustain driver 100 is continuously switched through the four states described above, then Vss will rise, with Vcc, to Vcc/2.
FIG. 3 is a schematic of a sustain driver 300, which serves as an exemplary implementation of the idealized circuit of FIG. 1. FIG. 4 is a timing diagram for several of the waveforms for sustain driver 300.
In FIG. 3, four transistors, T1, T2, T3 and T4, replace switches S1, S2, S3 and S4, respectively, of FIG. 1. A zener diode Z1 is connected to a node VG1 at a gate of transistor T1 to protect transistor T1. Likewise, zener diodes Z2 and Z3 are connected at nodes VG2 and VG3 to protect transistors T2 and T3. Transistors T1 and T3 have P-channels, and thus are turned on when a falling edge signal is provided at their gates. Transistors T2 and T4 have N-channels, and thus are turned on when a rising edge signal is provided at their gates.
A first driver, Driver 1, produces a signal that is coupled through a capacitor Cg1 to node VG3 to control transistor T1, and through a capacitor Cg2 to control transistor T2. T1 and T2 operate in a complementary fashion so that when T1 is on, T2 is off and vice-versa. A second driver, Driver 2, uses either a time constant of a resistor R1 and a capacitor C3, or a voltage fall at a node V1, to turn on transistor T4. Similarly, a third driver, Driver 3, uses either a time constant of a resistor R2 and a capacitor C4, or a voltage rise at a node V2, and provides a signal that is coupled through a capacitor Cg3 to turn on transistor T3. Two diodes, D3 and D4, are used to quickly turn off transistors T3 and T4. A generic driver 305 is shown to represent a typical internal configuration of Driver 1, Driver 2 and Driver 3.
State 1. A source 12 provides a control signal such that T1 is turned on and T2 is turned off. T3 is waiting to be turned on by the R2-C4 time constant or by the rise of voltage at node V2. T4 is turned off.
Through T1, Vss is applied to nodes V1 and A. Inductor L and panel capacitance Cp form a series resonant circuit that has a forcing voltage of Vss=Vcc/2. As a result of energy stored in inductor L, Vp rises past Vss approaching Vcc, at which point IL goes to zero.
Since Vp typically rises to 80% of Vcc, inductor L thereafter sees a forcing voltage, from the panel side, of Vp minus Vss. Negative current IL now flows out of the panel, back through inductor L, reverse biases D1 and charges the capacitance of T2. This reverse current, also known as flyback current, starts at time t1 in FIG. 4. A first flyback current causes a voltage flyback at nodes A and V2 to rise sharply. As the voltage at node V2 rises, C4 couples this rise to trigger Driver 3 to turn on T3.
The panel voltage Vp drops as energy is taken out of the panel by the flyback current and put back into inductor L between times t1 and t2. This energy, also known as flyback energy, is dissipated in T3, L, D2, and a diode DC2.
State 2. T3 is turned on to clamp Vp at Vcc and to provide a current path for any discharging “ON” pixel. Since energy was put into inductor L, negative current IL continues to flow from T3, and through inductor L, diode D2 and diode DC2, until the energy is dissipated. All of the aforesaid components are low loss components so the current decay is slow.
State 3. Source 12 provides the control signal such that T1 is turned off, T2 is turned on, T3 is turned off, and T4 remains off. Vp is approximately at Vcc, as panel capacitance Cp is fully charged. With T2 on, inductor L and panel capacitance Cp again form a series resonant circuit having a forcing voltage across inductor L of Vss=Vcc/2. As a result of energy stored in the inductor, Vp falls past Vss approaching ground, at which point IL is zero.
Since Vp typically falls to 20% of Vcc, inductor L thereafter sees a forcing voltage, toward the panel side, of Vss minus Vd. Positive current IL now flows out towards the panel drawing current through the inductor L, reverse biases diode D2 and discharges the capacitance of T1, pulling node V1 sharply to ground. A second flyback current through inductor L occurs at time t3 and is coupled through C3 to Driver 2, which turns on T4.
State 4. T4 clamps Vp to ground. On the opposite side of the plasma panel, another sustain driver (not shown in FIG. 3), which is identical to sustain driver 300, drives the opposite side of the panel to Vcc. If any pixels are “ON”, then a discharge current flows through T4.
FIG. 5 illustrates a sustain driver 500, which is disclosed in the Marcotte '018 patent as an improvement over sustain driver 100 of FIG. 1. FIG. 6 is a waveform diagram illustrating the operation of sustain driver 500.
In FIG. 5, a control network 20 has been added and is coupled to inductor L via a secondary winding 22. Control network 20 controls the conductivity states of switches S3 and S4. Control network 20 uses the voltage across inductor L (and secondary winding 22) to slowly close the output switch S3 after the output has risen past its halfway point. On the fall, switch S4 is slowly closed after the output descends past the halfway point. Diode DC2 and resistor R2 dampen one polarity of flyback current and a diode DC1 and resistor R1 dampen the opposite polarity flyback current. The conductivity states of S1 and S2 are controlled by circuitry (not shown in FIG. 5) that is responsive to input rise and fall of a logic control signal.
The operation of the four switching states of sustain driver 500 and timing diagrams of FIG. 6 are explained in detail below, where it is assumed that prior to State 1, the recovery voltage, Vss, is at Vcc/2, where Vcc is the sustain power supply voltage, Vp is at zero, S1 and S3 are open, and S2 and S4 are closed.
State 1. Switches S2 and S4 are opened, and switch S1 is closed. Vss is applied to node A. The voltage at node A is represented as voltage VA. Vc is the voltage across inductor L, i.e.,Vc=VP−VA. Since the current through inductor L is proportional to a time integral of the voltage across inductor L, current IL increases for the first half of State 1 and then decreases as panel voltage Vp rises above recovery voltage Vss, during the second half of State 1. Control network 20 senses across secondary winding 22, a voltage Vc′, which is proportional to Vc, and allows switch S3 to be turned on only after Vp has crossed Vss, the half-way point, and then only during the rise of Vp. In an ideal case, S3 is closed at the positive peak of Vc, time t1 and the instant the inductor L current IL equals zero (see FIG. 6). Briefly stated, S3 is to be closed and ready for full conduction when IL falls to zero at the end of State 1. This action enables the following flyback current through inductor L to be drawn from the Vcc supply, through S3, and not from the panel.
State 2. S1 and S3 remain closed, allowing S3 to be the source of both the current to sustain discharges in the panel and the flyback current that flows through inductor L. The flyback current brings voltage VA at node A up to Vcc. The energy induced into inductor L by the flyback current is dissipated by conduction through diodes D2, DC2 and resistor R2. The value of resistor R2 is chosen to dissipate the flyback energy before State 3.
State 3. S1 and S3 are opened, S4 remains open, and S2 is closed, bringing voltage VA at node A down to Vss. Vp is now greater than VA, causing negative current IL to flow proportional to the time integral of the voltage Vc across inductor L. Once the falling voltage Vp crosses the half-way point, Vc reverses polarity and control network 22 turns on switch S4 at the negative peak of Vc at time t3 in a manner similar to that described above for State 1.
State 4. S4 is closed while a second sustain driver 505 on the opposite side of the panel produces a sustain pulse that rises, discharges, and falls since S4 is part of the return path for the second sustain driver. When the voltage flyback occurs, the flyback current is drawn from S4 rather than from the panel, and returns the voltage Vc back to zero.
The energy recovery circuits disclosed in the Weber et al. '400 and Marcotte '018 patents employ a single resonant inductance, and therefore, these circuits provide sustain pulses that have symmetrical rise and fall times. As the gas discharge occurs at the completion of the rising transition, the rising transition must be fast and the turn-on of the pull up driver must be fully ON before the discharge occurs. However, the falling transition does not produce a discharge and the energy recovery efficiency of the panel can be increased if the edge rate is reduced. Nevertheless, the turn on timing of the pull down driver influences the efficiency of the panel and the generation of electrical noise.
There is a need for a circuit that provides for a PDP sustain pulse having a rise time that is not necessarily symmetrical to its fall time.